Problem:
When the 82574’s PCIe receive lane goesin and out of the L0s state, there might be
failures in the PCIe logic that result in a PCIehang or a PCIe uncorrectable error. These
issues have been reported when the 82574 is connected to the Intel®
5 Series Express
Chipset ports, but they do not occur on all PCIe switch ports.
Problematic connections to the 82574 can beidentified by clearing and polling the
Correctable Error Status register in the PCIeconfig space on the 82574 while passing LAN
traffic. Repeated assertions of the Bad DLLP and/or Replay Timer Timeout bits more than
once per minute indicate a problematic situation in which the following workaround
should be applied.
(中略)
Workaround:
Disable L0s in the Intel5 Series Express Chipset port connected to the 82574. Note
there is no requirement to disable ASPM-L1.
めも、未検証
http://pc.watch.impress.co.jp/docs/2009/0318/interface04.htm
L0s:Standby。L0にすぐ復帰可能
http://d.hatena.ne.jp/tsunokawa/20120912/p1
参考
http://blog.tiagomarques.com/2013/01/intel-8257382574-e1000e-driver-aspm-l1-bug-network-problem/
めも、未検証
